The present invention relates generally to a semiconductor memory device adopting a redundant circuit system for relieving defects in memory cells.
In semiconductor memories, such as DRAMs, defective cell rows and/or defective cell columns of a memory cell array are generally replaced with redundant cell rows and/or redundant cell columns to be relieved. Hereinafter, cell rows and cell columns are simply referred to as rows and columns, respectively.
In order to achieve this, a cell array including redundant rows and redundant columns, together with an address comparator circuit, is provided in a chip.
In the address comparator circuit, a defective address is programmed on the basis of test (die sorting test) results performed in a wafer state. Then, the address comparator circuit has the function of outputting a substitute signal when an inputted address is coincident with the programmed defective address, to select a redundant row or a redundant column in place of a defective row or a defective column. Hereinafter, a redundant row or a redundant column is referred as a redundant element if distinction is not necessary.
A typical defective address storing circuit of the address comparator circuit uses a fuse circuit wherein a programming is carried out by laser light. After the programming in the address comparator circuit, non-defective memory chips are cut away from a wafer to be assembled into packages. Thereafter, a stress test is carried out, and finally, a memory test (a shipping test) is carried out whether the memory is normally operated. Only non-defective memories having passed the memory test are shipped, and the rest of the memories are discarded.
Conventionally, a fuse element blown by laser light has been used as the address comparator circuit, and there has been no means for relieving defects found in a test after assembly.
Therefore, in order to improve the yields of memories, it is important to precisely carry out a wafer process to enhance the yields in a die sorting test and to reduce the number of chips discarded by a shipping test. However, conventional semiconductor memories are not provided with any means for relieving defects generated after assembly.